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| # | Category | Description | Detection Method | Fix | |---|----------|-------------|------------------|-----| | 1 | DFE Control‑Path | : A race condition between CFG write and DFE execution caused a one‑cycle stall that violated the no‑interleaved‑CFG property. | Formal model checking (counter‑example of 7‑cycle window). | Inserted a pipeline barrier after each CFG write. | | 2 | Core Pipeline | ROB‑Overflow : Under extreme branch‑misprediction bursts, the ROB could overflow before retire. | Coverage‑directed random simulation (2 M instruction bursts). | Increased ROB size to 224 entries and added early‑retire heuristic. | | 3 | Memory Coherence | Shared‑Dirty Violation : Simultaneous dirty state of a cache line in core and DFE caused coherence protocol dead‑lock. | Emulation (hardware‑accelerated stress test). | Added a dirty‑interlock arbitration in the L2 directory. | | 4 | Power‑Gating | Spurious Wake‑up : Power‑gated DFE domain sometimes woke up due to spurious wake‑signal toggling during low‑power entry. | Formal property “no‑wake‑up‑without‑request”. | Implemented glitch‑filtering on wake‑signal net. |