Synopsys Design Compiler Tutorial 2021 ((full))

Directories where DC searches for design files and libraries.

By 2021, the focus was heavily on or DC Topographical (DC-T) , which offers improved correlation between synthesis and physical layout (IC Compiler/ICC2), often within 10% accuracy. Synopsys Design Compiler Tutorial 2021: From RTL to Netlist 1. Introduction to Design Compiler (2021 Edition)

# Set operating conditions (worst case for setup) set_operating_conditions -max "WCCOM" -max_library $target_library synopsys design compiler tutorial 2021

# Generate a summary of setup and hold timing configurations report_constraint -all_violators # Generate a detailed path report for the critical timing path report_timing -delay_type max -max_paths 1 # Generate a report showing cell, combinational, and total area report_area > area_report.txt # Generate an estimated power consumption report report_power > power_report.txt Use code with caution.

Synopsys Design Compiler has a rich history, with several editions serving different design needs. As of 2021, the most relevant versions for a standard user were: Directories where DC searches for design files and libraries

# In your .bashrc or .cshrc setenv SYNOPSYS_HOME /tools/synopsys/2021.03 setenv PATH $SYNOPSYS_HOME/bin:$PATH setenv SNPSLMD_LICENSE_FILE 27000@license_server setenv LM_LICENSE_FILE 27000@license_server

1. Introduction to Logic Synthesis with Synopsys Design Compiler Introduction to Design Compiler (2021 Edition) # Set

# Define synthetic library (for DW architectures) set synthetic_library [list standard.sldb]

# Create a work directory for intermediate files define_design_lib WORK -path ./WORK # Analyze the RTL source files (syntax checking) analyze -format sutwerilog top_module.sv controller.sv datapath.sv # Elaborate the top-level design (builds generic logic structure) elaborate top_module -parameters "DATA_WIDTH=32" # Set the current design context current_design top_module # Resolve design references link Use code with caution. 4. Applying Timing and Design Constraints

set designer "YOUR_NAME" set company "YOUR_COMPANY" set search_path [list . /path/to/your/libraries] set target_library "your_technology.db" set link_library "* $target_library" set symbol_library "your_technology.sdb" define_design_lib work -path ./WORK

# Don't optimize area beyond 95% of initial estimate set_max_area 0